The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
In semiconductor manufacturing, vias are formed in the Back-End-Of-Line (BEOL) processing for a semiconductor device as part of an interconnect structure to connect various conductive features (e.g., conductive lines) formed in different layers (e.g., inter-metal dielectric layers) of the semiconductor device. Vias may be formed by etching the dielectric layer(s) to form via openings first, cleaning the via openings, then filling the via openings with conductive material(s) such as copper, tungsten, or other suitable conductive material. However, manufacturing of the vias has problems that need to be addressed.